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Design for manufacturability through design-process integration IV : 24-25 February 2010, San Jose, California, United States / |
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ISBN/ISSN:
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9780819480552 |
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中图分类法
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TN402-532 |
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题名:
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Design for manufacturability through design-process integration IV [24-25 February 2010, San Jose, California, United States ] |
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出版发行:
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Bellingham, Wash. : SPIE, c2010. |
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载体形态:
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1 v. (various pagings) : ill. ; 28 cm. |
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主题词:
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Integrated circuits Design and construction |
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主题词:
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Integrated circuits Defects Analysis |
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主题词:
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Semiconductors Design and construction |
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主题词:
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Semiconductor wafers Defects Analysis |
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主题词:
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Microelectronics industry Quality control |
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主题词:
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Quality control |
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主要责任者:
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Rieger, Michael L. |
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主要责任者:
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Thiele, Joerg. |
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HEA| |01387nam a2200289 a 4500 001| |022010002485 005| |20101126141532.5 008| |101126s2008 waua b 101 0 eng 020| |▼a9780819480552 040| |▼aWHUT▼cWHUT 093| |▼aTN402-532▼24 245|00|▼aDesign for manufacturability- | | through design-process integr- | |ation IV :▼b24-25 February 201- | |0, San Jose, California, Unite- | |d States /▼cMichael L. Rieger,- | | Joerg Thiele, editors ; spons- | |ored by SPIE ; cooperating org- | |anization, SEMATECH (United States). 260| |▼aBellingham, Wash. :▼bSPIE,▼cc2010. 300| |▼a1 v. (various pagings) :▼bil- | |l. ;▼c28 cm. 490|1 |▼aProceedings of SPIE,▼x0277-7- | |86X ;▼vv. 7641 504| |▼aIncludes bibliographical ref- | |erences and author index. 650| 0|▼aIntegrated circuits▼xDesign - | |and construction▼vCongresses. 650| 0|▼aIntegrated circuits▼xDefects- | |▼xAnalysis▼vCongresses. 650| 0|▼aSemiconductors▼xDesign and c- | |onstruction▼vCongresses. 650| 0|▼aSemiconductor wafers▼xDefect- | |s▼xAnalysis▼vCongresses. 650| 0|▼aMicroelectronics industry▼xQ- | |uality control▼vCongresses. 650| 0|▼aQuality control▼vCongresses. 700|1 |▼aRieger, Michael L. 700|1 |▼aThiele, Joerg. 710|2 |▼aSociety of Photo-optical Ins- | |trumentation Engineers. 710|2 |▼aInternational SEMATECH. 830| 0|▼aProceedings of SPIE－－the Int- | |ernational Society for Optical- | | Engineering ;▼vv. 6925.
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